Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Presto compilation completed successfully.
Loading db file '/net/plato.ee.virginia.edu/users/wz6pc/synopsys/syn_tut/dc/ref/models/saed90nm_typ_ht.db'
Loading db file '/app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/dw_foundation.sldb'
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./RAS.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/RAS.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/RAS.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/RAS.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/RAS.v
Searching for ../ref/models/RAS.v
Searching for ../source/Core-1/RAS.v
Searching for ../source/Core-1/fetch/RAS.v
Searching for ./BTB.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/BTB.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/BTB.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/BTB.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/BTB.v
Searching for ../ref/models/BTB.v
Searching for ../source/Core-1/BTB.v
Searching for ../source/Core-1/fetch/BTB.v
Searching for ./SelectInst.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SelectInst.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SelectInst.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SelectInst.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SelectInst.v
Searching for ../ref/models/SelectInst.v
Searching for ../source/Core-1/SelectInst.v
Searching for ../source/Core-1/fetch/SelectInst.v
Searching for ./BranchPrediction_2-bit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/BranchPrediction_2-bit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/BranchPrediction_2-bit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/BranchPrediction_2-bit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/BranchPrediction_2-bit.v
Searching for ../ref/models/BranchPrediction_2-bit.v
Searching for ../source/Core-1/BranchPrediction_2-bit.v
Searching for ../source/Core-1/fetch/BranchPrediction_2-bit.v
Searching for ./FetchStage1.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FetchStage1.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FetchStage1.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FetchStage1.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FetchStage1.v
Searching for ../ref/models/FetchStage1.v
Searching for ../source/Core-1/FetchStage1.v
Searching for ../source/Core-1/fetch/FetchStage1.v
Searching for ./Fetch1Fetch2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/Fetch1Fetch2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/Fetch1Fetch2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/Fetch1Fetch2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/Fetch1Fetch2.v
Searching for ../ref/models/Fetch1Fetch2.v
Searching for ../source/Core-1/Fetch1Fetch2.v
Searching for ../source/Core-1/fetch/Fetch1Fetch2.v
Searching for ./FetchStage2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FetchStage2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FetchStage2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FetchStage2.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FetchStage2.v
Searching for ../ref/models/FetchStage2.v
Searching for ../source/Core-1/FetchStage2.v
Searching for ../source/Core-1/fetch/FetchStage2.v
Searching for ./Fetch2Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/Fetch2Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/Fetch2Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/Fetch2Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/Fetch2Decode.v
Searching for ../ref/models/Fetch2Decode.v
Searching for ../source/Core-1/Fetch2Decode.v
Searching for ../source/Core-1/fetch/Fetch2Decode.v
Searching for ./CtrlQueue.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/CtrlQueue.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/CtrlQueue.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/CtrlQueue.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/CtrlQueue.v
Searching for ../ref/models/CtrlQueue.v
Searching for ../source/Core-1/CtrlQueue.v
Searching for ../source/Core-1/fetch/CtrlQueue.v
Searching for ./L1ICache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/L1ICache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/L1ICache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/L1ICache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/L1ICache.v
Searching for ../ref/models/L1ICache.v
Searching for ../source/Core-1/L1ICache.v
Searching for ../source/Core-1/fetch/L1ICache.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/fetch/RAS.v
Compiling source file ../source/Core-1/fetch/BTB.v
Compiling source file ../source/Core-1/fetch/SelectInst.v
Compiling source file ../source/Core-1/fetch/BranchPrediction_2-bit.v
Compiling source file ../source/Core-1/fetch/FetchStage1.v
Compiling source file ../source/Core-1/fetch/Fetch1Fetch2.v
Compiling source file ../source/Core-1/fetch/FetchStage2.v
Compiling source file ../source/Core-1/fetch/Fetch2Decode.v
Compiling source file ../source/Core-1/fetch/CtrlQueue.v
Compiling source file ../source/Core-1/fetch/L1ICache.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/Decode.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/Decode.v
Searching for ../ref/models/Decode.v
Searching for ../source/Core-1/Decode.v
Searching for ../source/Core-1/fetch/Decode.v
Searching for ../source/Core-1/decode/Decode.v
Searching for ./Decode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/Decode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/Decode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/Decode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/Decode_PISA.v
Searching for ../ref/models/Decode_PISA.v
Searching for ../source/Core-1/Decode_PISA.v
Searching for ../source/Core-1/fetch/Decode_PISA.v
Searching for ../source/Core-1/decode/Decode_PISA.v
Searching for ./PreDecode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/PreDecode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/PreDecode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/PreDecode_PISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/PreDecode_PISA.v
Searching for ../ref/models/PreDecode_PISA.v
Searching for ../source/Core-1/PreDecode_PISA.v
Searching for ../source/Core-1/fetch/PreDecode_PISA.v
Searching for ../source/Core-1/decode/PreDecode_PISA.v
Searching for ./InstructionBuffer.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/InstructionBuffer.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/InstructionBuffer.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/InstructionBuffer.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/InstructionBuffer.v
Searching for ../ref/models/InstructionBuffer.v
Searching for ../source/Core-1/InstructionBuffer.v
Searching for ../source/Core-1/fetch/InstructionBuffer.v
Searching for ../source/Core-1/decode/InstructionBuffer.v
Searching for ./InstBufRename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/InstBufRename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/InstBufRename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/InstBufRename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/InstBufRename.v
Searching for ../ref/models/InstBufRename.v
Searching for ../source/Core-1/InstBufRename.v
Searching for ../source/Core-1/fetch/InstBufRename.v
Searching for ../source/Core-1/decode/InstBufRename.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/decode/Decode.v
Compiling source file ../source/Core-1/decode/Decode_PISA.v
Compiling source file ../source/Core-1/decode/PreDecode_PISA.v
Compiling source file ../source/Core-1/decode/InstructionBuffer.v
Compiling source file ../source/Core-1/decode/InstBufRename.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./SpecFreeList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SpecFreeList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SpecFreeList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SpecFreeList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SpecFreeList.v
Searching for ../ref/models/SpecFreeList.v
Searching for ../source/Core-1/SpecFreeList.v
Searching for ../source/Core-1/fetch/SpecFreeList.v
Searching for ../source/Core-1/decode/SpecFreeList.v
Searching for ../source/Core-1/rename/SpecFreeList.v
Searching for ./RenameMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/RenameMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/RenameMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/RenameMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/RenameMapTable.v
Searching for ../ref/models/RenameMapTable.v
Searching for ../source/Core-1/RenameMapTable.v
Searching for ../source/Core-1/fetch/RenameMapTable.v
Searching for ../source/Core-1/decode/RenameMapTable.v
Searching for ../source/Core-1/rename/RenameMapTable.v
Searching for ./Rename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/Rename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/Rename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/Rename.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/Rename.v
Searching for ../ref/models/Rename.v
Searching for ../source/Core-1/Rename.v
Searching for ../source/Core-1/fetch/Rename.v
Searching for ../source/Core-1/decode/Rename.v
Searching for ../source/Core-1/rename/Rename.v
Searching for ./RenameDispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/RenameDispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/RenameDispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/RenameDispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/RenameDispatch.v
Searching for ../ref/models/RenameDispatch.v
Searching for ../source/Core-1/RenameDispatch.v
Searching for ../source/Core-1/fetch/RenameDispatch.v
Searching for ../source/Core-1/decode/RenameDispatch.v
Searching for ../source/Core-1/rename/RenameDispatch.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/rename/SpecFreeList.v
Compiling source file ../source/Core-1/rename/RenameMapTable.v
Compiling source file ../source/Core-1/rename/Rename.v
Warning:  ../source/Core-1/rename/Rename.v:218: the undeclared symbol 'checkPointedRMT' assumed to have the default net type, which is 'wire'. (VER-936)
Compiling source file ../source/Core-1/rename/RenameDispatch.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./Dispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/Dispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/Dispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/Dispatch.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/Dispatch.v
Searching for ../ref/models/Dispatch.v
Searching for ../source/Core-1/Dispatch.v
Searching for ../source/Core-1/fetch/Dispatch.v
Searching for ../source/Core-1/decode/Dispatch.v
Searching for ../source/Core-1/rename/Dispatch.v
Searching for ../source/Core-1/dispatch/Dispatch.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/dispatch/Dispatch.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
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Compiling source file ../source/Core-1/FabScalarParam.v
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Presto compilation completed successfully.
Running PRESTO HDLC
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Compiling source file ../source/Core-1/FabScalarParam.v
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Compiling source file ../source/Core-1/execute/AgenLsu.v
Compiling source file ../source/Core-1/execute/Execute.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
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Searching for ../source/Core-1/memory/CommitLoad.v
Searching for ./CommitStore.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/CommitStore.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/CommitStore.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/CommitStore.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/CommitStore.v
Searching for ../ref/models/CommitStore.v
Searching for ../source/Core-1/CommitStore.v
Searching for ../source/Core-1/fetch/CommitStore.v
Searching for ../source/Core-1/decode/CommitStore.v
Searching for ../source/Core-1/rename/CommitStore.v
Searching for ../source/Core-1/dispatch/CommitStore.v
Searching for ../source/Core-1/issue/CommitStore.v
Searching for ../source/Core-1/execute/CommitStore.v
Searching for ../source/Core-1/writeback/CommitStore.v
Searching for ../source/Core-1/memory/CommitStore.v
Searching for ./LoadStoreUnit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/LoadStoreUnit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/LoadStoreUnit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/LoadStoreUnit.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/LoadStoreUnit.v
Searching for ../ref/models/LoadStoreUnit.v
Searching for ../source/Core-1/LoadStoreUnit.v
Searching for ../source/Core-1/fetch/LoadStoreUnit.v
Searching for ../source/Core-1/decode/LoadStoreUnit.v
Searching for ../source/Core-1/rename/LoadStoreUnit.v
Searching for ../source/Core-1/dispatch/LoadStoreUnit.v
Searching for ../source/Core-1/issue/LoadStoreUnit.v
Searching for ../source/Core-1/execute/LoadStoreUnit.v
Searching for ../source/Core-1/writeback/LoadStoreUnit.v
Searching for ../source/Core-1/memory/LoadStoreUnit.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/memory/DispatchedLoad.v
Compiling source file ../source/Core-1/memory/DispatchedStore.v
Compiling source file ../source/Core-1/memory/CommitLoad.v
Compiling source file ../source/Core-1/memory/CommitStore.v
Compiling source file ../source/Core-1/memory/LoadStoreUnit.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./WriteBack.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/WriteBack.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/WriteBack.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/WriteBack.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/WriteBack.v
Searching for ../ref/models/WriteBack.v
Searching for ../source/Core-1/WriteBack.v
Searching for ../source/Core-1/fetch/WriteBack.v
Searching for ../source/Core-1/decode/WriteBack.v
Searching for ../source/Core-1/rename/WriteBack.v
Searching for ../source/Core-1/dispatch/WriteBack.v
Searching for ../source/Core-1/issue/WriteBack.v
Searching for ../source/Core-1/execute/WriteBack.v
Searching for ../source/Core-1/writeback/WriteBack.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/writeback/WriteBack.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./ActiveList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/ActiveList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/ActiveList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/ActiveList.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/ActiveList.v
Searching for ../ref/models/ActiveList.v
Searching for ../source/Core-1/ActiveList.v
Searching for ../source/Core-1/fetch/ActiveList.v
Searching for ../source/Core-1/decode/ActiveList.v
Searching for ../source/Core-1/rename/ActiveList.v
Searching for ../source/Core-1/dispatch/ActiveList.v
Searching for ../source/Core-1/issue/ActiveList.v
Searching for ../source/Core-1/execute/ActiveList.v
Searching for ../source/Core-1/writeback/ActiveList.v
Searching for ../source/Core-1/memory/ActiveList.v
Searching for ../source/Core-1/retire/ActiveList.v
Searching for ./ArchMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/ArchMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/ArchMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/ArchMapTable.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/ArchMapTable.v
Searching for ../ref/models/ArchMapTable.v
Searching for ../source/Core-1/ArchMapTable.v
Searching for ../source/Core-1/fetch/ArchMapTable.v
Searching for ../source/Core-1/decode/ArchMapTable.v
Searching for ../source/Core-1/rename/ArchMapTable.v
Searching for ../source/Core-1/dispatch/ArchMapTable.v
Searching for ../source/Core-1/issue/ArchMapTable.v
Searching for ../source/Core-1/execute/ArchMapTable.v
Searching for ../source/Core-1/writeback/ArchMapTable.v
Searching for ../source/Core-1/memory/ArchMapTable.v
Searching for ../source/Core-1/retire/ArchMapTable.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/retire/ActiveList.v
Compiling source file ../source/Core-1/retire/ArchMapTable.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./L1DataCache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/L1DataCache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/L1DataCache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/L1DataCache.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/L1DataCache.v
Searching for ../ref/models/L1DataCache.v
Searching for ../source/Core-1/L1DataCache.v
Searching for ../source/Core-1/fetch/L1DataCache.v
Searching for ../source/Core-1/decode/L1DataCache.v
Searching for ../source/Core-1/rename/L1DataCache.v
Searching for ../source/Core-1/dispatch/L1DataCache.v
Searching for ../source/Core-1/issue/L1DataCache.v
Searching for ../source/Core-1/execute/L1DataCache.v
Searching for ../source/Core-1/writeback/L1DataCache.v
Searching for ../source/Core-1/memory/L1DataCache.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/memory/L1DataCache.v
Presto compilation completed successfully.
Running PRESTO HDLC
Searching for ./FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FabScalarParam.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FabScalarParam.v
Searching for ../ref/models/FabScalarParam.v
Searching for ../source/Core-1/FabScalarParam.v
Searching for ./SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/SimpleScalar_ISA.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/SimpleScalar_ISA.v
Searching for ../ref/models/SimpleScalar_ISA.v
Searching for ../source/Core-1/SimpleScalar_ISA.v
Searching for ../source/Core-1/fetch/SimpleScalar_ISA.v
Searching for ../source/Core-1/decode/SimpleScalar_ISA.v
Searching for ../source/Core-1/rename/SimpleScalar_ISA.v
Searching for ../source/Core-1/dispatch/SimpleScalar_ISA.v
Searching for ../source/Core-1/issue/SimpleScalar_ISA.v
Searching for ../source/Core-1/execute/SimpleScalar_ISA.v
Searching for ../source/Core-1/writeback/SimpleScalar_ISA.v
Searching for ../source/Core-1/memory/SimpleScalar_ISA.v
Searching for ../source/Core-1/retire/SimpleScalar_ISA.v
Searching for ../source/Core-1/pmems/SimpleScalar_ISA.v
Searching for ../source/Core-1/ISA/SimpleScalar_ISA.v
Searching for ./Interface.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/Interface.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/Interface.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/Interface.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/Interface.v
Searching for ../ref/models/Interface.v
Searching for ../source/Core-1/Interface.v
Searching for ../source/Core-1/fetch/Interface.v
Searching for ../source/Core-1/decode/Interface.v
Searching for ../source/Core-1/rename/Interface.v
Searching for ../source/Core-1/dispatch/Interface.v
Searching for ../source/Core-1/issue/Interface.v
Searching for ../source/Core-1/execute/Interface.v
Searching for ../source/Core-1/writeback/Interface.v
Searching for ../source/Core-1/memory/Interface.v
Searching for ../source/Core-1/retire/Interface.v
Searching for ../source/Core-1/pmems/Interface.v
Searching for ../source/Core-1/ISA/Interface.v
Searching for ../source/Core-1/fabscalar/Interface.v
Searching for ./FABSCALAR.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/FABSCALAR.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn/FABSCALAR.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver/FABSCALAR.v
Searching for /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver/FABSCALAR.v
Searching for ../ref/models/FABSCALAR.v
Searching for ../source/Core-1/FABSCALAR.v
Searching for ../source/Core-1/fetch/FABSCALAR.v
Searching for ../source/Core-1/decode/FABSCALAR.v
Searching for ../source/Core-1/rename/FABSCALAR.v
Searching for ../source/Core-1/dispatch/FABSCALAR.v
Searching for ../source/Core-1/issue/FABSCALAR.v
Searching for ../source/Core-1/execute/FABSCALAR.v
Searching for ../source/Core-1/writeback/FABSCALAR.v
Searching for ../source/Core-1/memory/FABSCALAR.v
Searching for ../source/Core-1/retire/FABSCALAR.v
Searching for ../source/Core-1/pmems/FABSCALAR.v
Searching for ../source/Core-1/ISA/FABSCALAR.v
Searching for ../source/Core-1/fabscalar/FABSCALAR.v
Compiling source file ../source/Core-1/FabScalarParam.v
Compiling source file ../source/Core-1/ISA/SimpleScalar_ISA.v
Compiling source file ../source/Core-1/fabscalar/Interface.v
Compiling source file ../source/Core-1/fabscalar/FABSCALAR.v
Presto compilation completed successfully.
Loading db file '/app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/gtech.db'
Loading db file '/app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn/standard.sldb'
  Loading link library 'saed90nm_typ_ht'
  Loading link library 'gtech'
Running PRESTO HDLC
Presto compilation completed successfully.
Elaborated 1 design.
Current design is now 'FABSCALAR'.
Information: Building the design 'Interface'. (HDL-193)

Inferred memory devices in process
	in routine Interface line 33 in file
		'../source/Core-1/fabscalar/Interface.v'.
==================================================================================
|     Register Name      |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
==================================================================================
| missAddrL1ICache_o_reg | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
| wrL1ICacheEnable_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|  wrAddrL1ICache_o_reg  | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
| wrBlockL1ICache_o_reg  | Flip-flop |  256  |  Y  | N  | N  | N  | N  | N  | N  |
|   missL1ICache_o_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
==================================================================================
Presto compilation completed successfully.
Information: Building the design 'FetchStage1'. (HDL-193)

Statistics for case statements in always block at line 246 in file
	'../source/Core-1/fetch/FetchStage1.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           266            |     no/auto      |
===============================================

Statistics for case statements in always block at line 315 in file
	'../source/Core-1/fetch/FetchStage1.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           319            |     no/auto      |
===============================================

Statistics for case statements in always block at line 361 in file
	'../source/Core-1/fetch/FetchStage1.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           364            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine FetchStage1 line 421 in file
		'../source/Core-1/fetch/FetchStage1.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       PC_reg        | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'Fetch1Fetch2'. (HDL-193)

Inferred memory devices in process
	in routine Fetch1Fetch2 line 72 in file
		'../source/Core-1/fetch/Fetch1Fetch2.v'.
===================================================================================
|      Register Name      |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===================================================================================
|    prediction3_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     fs1Ready_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|        pc_o_reg         | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
| instructionBundle_o_reg | Flip-flop |  256  |  Y  | N  | N  | N  | N  | N  | N  |
|      btbHit0_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    targetAddr0_o_reg    | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    prediction0_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|      btbHit1_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    targetAddr1_o_reg    | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    prediction1_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|      btbHit2_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    targetAddr2_o_reg    | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    prediction2_o_reg    | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|      btbHit3_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    targetAddr3_o_reg    | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
===================================================================================
Presto compilation completed successfully.
Information: Building the design 'FetchStage2'. (HDL-193)

Statistics for case statements in always block at line 216 in file
	'../source/Core-1/fetch/FetchStage2.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           250            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine FetchStage2 line 216 in file
		'../source/Core-1/fetch/FetchStage2.v'.
===========================================================================
|    Register Name    | Type  | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
|     callPC_reg      | Latch |  32   |  Y  | N  | N  | N  | -  | -  | -  |
|   targetAddr_reg    | Latch |  32   |  Y  | N  | N  | N  | -  | -  | -  |
===========================================================================
Presto compilation completed successfully.
Information: Building the design 'Fetch2Decode'. (HDL-193)

Inferred memory devices in process
	in routine Fetch2Decode line 58 in file
		'../source/Core-1/fetch/Fetch2Decode.v'.
==================================================================================
|     Register Name      |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
==================================================================================
|    updateDir_o_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     updateEn_o_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|     updatePC_o_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
| updateTargetAddr_o_reg | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|  updateCtrlType_o_reg  | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
==================================================================================

Inferred memory devices in process
	in routine Fetch2Decode line 79 in file
		'../source/Core-1/fetch/Fetch2Decode.v'.
===================================================================================
|      Register Name      |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===================================================================================
|    inst3Packet_o_reg    | Flip-flop |  133  |  Y  | N  | N  | N  | N  | N  | N  |
|     fs2Ready_o_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| instruction0Valid_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    inst0Packet_o_reg    | Flip-flop |  133  |  Y  | N  | N  | N  | N  | N  | N  |
| instruction1Valid_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    inst1Packet_o_reg    | Flip-flop |  133  |  Y  | N  | N  | N  | N  | N  | N  |
| instruction2Valid_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    inst2Packet_o_reg    | Flip-flop |  133  |  Y  | N  | N  | N  | N  | N  | N  |
| instruction3Valid_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===================================================================================
Presto compilation completed successfully.
Information: Building the design 'Decode'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)

Inferred memory devices in process
	in routine Decode line 165 in file
		'../source/Core-1/decode/Decode.v'.
===========================================================================
|    Register Name    | Type  | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
| decodedPacket_f_reg | Latch |  27   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  27   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  27   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  27   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  27   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  27   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  27   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  29   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  49   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |  48   |  Y  | N  | N  | N  | -  | -  | -  |
| decodedPacket_f_reg | Latch |   7   |  N  | N  | N  | N  | -  | -  | -  |
===========================================================================
Presto compilation completed successfully.
Information: Building the design 'InstructionBuffer'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/decode/InstructionBuffer.v:181: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/decode/InstructionBuffer.v:216: signed to unsigned conversion occurs. (VER-318)

Inferred memory devices in process
	in routine InstructionBuffer line 195 in file
		'../source/Core-1/decode/InstructionBuffer.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     headPtr_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine InstructionBuffer line 244 in file
		'../source/Core-1/decode/InstructionBuffer.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     tailPtr_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine InstructionBuffer line 290 in file
		'../source/Core-1/decode/InstructionBuffer.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    instCount_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'InstBufRename'. (HDL-193)

Inferred memory devices in process
	in routine InstBufRename line 54 in file
		'../source/Core-1/decode/InstBufRename.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
|   branchCount_o_reg   | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
| instBufferReady_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| decodedPacket0_o_reg  | Flip-flop |  126  |  Y  | N  | N  | N  | N  | N  | N  |
| decodedPacket1_o_reg  | Flip-flop |  126  |  Y  | N  | N  | N  | N  | N  | N  |
| decodedPacket2_o_reg  | Flip-flop |  126  |  Y  | N  | N  | N  | N  | N  | N  |
| decodedPacket3_o_reg  | Flip-flop |  126  |  Y  | N  | N  | N  | N  | N  | N  |
=================================================================================
Presto compilation completed successfully.
Information: Building the design 'Rename'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'RenameDispatch'. (HDL-193)

Inferred memory devices in process
	in routine RenameDispatch line 60 in file
		'../source/Core-1/rename/RenameDispatch.v'.
================================================================================
|    Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
================================================================================
| renamedPacket3_o_reg | Flip-flop |  145  |  Y  | N  | N  | N  | N  | N  | N  |
|  renameReady_o_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| renamedPacket0_o_reg | Flip-flop |  145  |  Y  | N  | N  | N  | N  | N  | N  |
| renamedPacket1_o_reg | Flip-flop |  145  |  Y  | N  | N  | N  | N  | N  | N  |
| renamedPacket2_o_reg | Flip-flop |  145  |  Y  | N  | N  | N  | N  | N  | N  |
================================================================================
Presto compilation completed successfully.
Information: Building the design 'Dispatch'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/dispatch/Dispatch.v:252: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/dispatch/Dispatch.v:260: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/dispatch/Dispatch.v:268: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/dispatch/Dispatch.v:276: signed to unsigned conversion occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'IssueQueue'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/issue/IssueQueue.v:692: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:719: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:724: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:729: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:734: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:765: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:765: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:773: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:773: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:796: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:796: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:834: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:834: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:842: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:842: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:948: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:952: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:956: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQueue.v:960: signed to unsigned conversion occurs. (VER-318)

Inferred memory devices in process
	in routine IssueQueue line 853 in file
		'../source/Core-1/issue/IssueQueue.v'.
================================================================================
|    Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
================================================================================
|   ISSUEQ_VALID_reg   | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_SCHEDULED_reg | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
================================================================================

Inferred memory devices in process
	in routine IssueQueue line 880 in file
		'../source/Core-1/issue/IssueQueue.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    ISSUEQ_FU_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine IssueQueue line 933 in file
		'../source/Core-1/issue/IssueQueue.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   BRANCH_MASK_reg   | Flip-flop |  128  |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine IssueQueue line 978 in file
		'../source/Core-1/issue/IssueQueue.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| SRC1_REG_VALID_reg  | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
| SRC0_REG_VALID_reg  | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|  IssueQueue/552  |   32   |    4    |      5       | N  |
|  IssueQueue/552  |   4    |   36    |      2       | N  |
|  IssueQueue/553  |   32   |    4    |      5       | N  |
|  IssueQueue/554  |   32   |    4    |      5       | N  |
|  IssueQueue/555  |   32   |    4    |      5       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'IssueqRegRead'. (HDL-193)

Inferred memory devices in process
	in routine IssueqRegRead line 58 in file
		'../source/Core-1/issue/issueqRegRead.v'.
================================================================================
|    Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
================================================================================
| grantedValid2_o_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| grantedPacket2_o_reg | Flip-flop |  139  |  Y  | N  | N  | N  | N  | N  | N  |
| grantedPacket1_o_reg | Flip-flop |  139  |  Y  | N  | N  | N  | N  | N  | N  |
| grantedPacket0_o_reg | Flip-flop |  139  |  Y  | N  | N  | N  | N  | N  | N  |
| grantedValid3_o_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| grantedPacket3_o_reg | Flip-flop |  139  |  Y  | N  | N  | N  | N  | N  | N  |
| grantedValid0_o_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| grantedValid1_o_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
================================================================================
Presto compilation completed successfully.
Information: Building the design 'RegRead'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)

Statistics for case statements in always block at line 440 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           442            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 451 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           453            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 462 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           464            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 473 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           475            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 484 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           486            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 495 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           497            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 506 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           508            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 517 in file
	'../source/Core-1/issue/RegRead.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           519            |    auto/auto     |
===============================================

Inferred memory devices in process
	in routine RegRead line 574 in file
		'../source/Core-1/issue/RegRead.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  PHY_REG_VALID_reg  | Flip-flop |  96   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|   RegRead/545    |   4    |    4    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'RegReadExecute'. (HDL-193)

Inferred memory devices in process
	in routine RegReadExecute line 284 in file
		'../source/Core-1/issue/RegReadExecute.v'.
================================================================================
|    Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
================================================================================
| fuPacketValid1_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
| fuPacketValid3_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|   fuPacket2_o_reg    | Flip-flop |  196  |  Y  | N  | N  | N  | N  | N  | N  |
| fuPacketValid2_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|   fuPacket1_o_reg    | Flip-flop |  125  |  Y  | N  | N  | N  | N  | N  | N  |
|   fuPacket3_o_reg    | Flip-flop |  130  |  Y  | N  | N  | N  | N  | N  | N  |
| fuPacketValid0_o_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|   fuPacket0_o_reg    | Flip-flop |  125  |  Y  | N  | N  | N  | N  | N  | N  |
================================================================================
Presto compilation completed successfully.
Information: Building the design 'Execute'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'WriteBack'. (HDL-193)

Inferred memory devices in process
	in routine WriteBack line 279 in file
		'../source/Core-1/writeback/WriteBack.v'.
=================================================================================
|     Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
=================================================================================
|  exePacketValid1_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|  lsuPacketValid0_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    lsuPacket0_reg     | Flip-flop |  63   |  Y  | N  | N  | N  | N  | N  | N  |
|  exePacketValid2_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    exePacket2_reg     | Flip-flop |  97   |  Y  | N  | N  | N  | N  | N  | N  |
| ldViolationPacket_reg | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|    exePacket0_reg     | Flip-flop |  60   |  Y  | N  | N  | N  | N  | N  | N  |
|  exePacketValid0_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    exePacket1_reg     | Flip-flop |  60   |  Y  | N  | N  | N  | N  | N  | N  |
=================================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|  WriteBack/191   |   4    |    4    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'AgenLsu'. (HDL-193)

Inferred memory devices in process
	in routine AgenLsu line 67 in file
		'../source/Core-1/execute/AgenLsu.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   exePacket3_reg    | Flip-flop |  109  |  Y  | N  | N  | N  | N  | N  | N  |
| exePacketValid3_reg | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|    AgenLsu/60    |   4    |    1    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'LSU'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:342: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:342: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:351: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:351: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:393: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:434: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:434: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:443: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:443: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:507: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/memory/LoadStoreUnit.v:629: signed to unsigned conversion occurs. (VER-318)

Statistics for case statements in always block at line 637 in file
	'../source/Core-1/memory/LoadStoreUnit.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           658            |     no/auto      |
===============================================

Statistics for case statements in always block at line 788 in file
	'../source/Core-1/memory/LoadStoreUnit.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           833            |     no/auto      |
|           1009           |     no/auto      |
===============================================

Statistics for case statements in always block at line 1147 in file
	'../source/Core-1/memory/LoadStoreUnit.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           1200           |     no/auto      |
===============================================

Statistics for case statements in always block at line 1518 in file
	'../source/Core-1/memory/LoadStoreUnit.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           1529           |     no/auto      |
===============================================

Inferred memory devices in process
	in routine LSU line 529 in file
		'../source/Core-1/memory/LoadStoreUnit.v'.
===========================================================================
|    Register Name    | Type  | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
|   lsuPacket0_reg    | Latch |  63   |  Y  | N  | N  | N  | -  | -  | -  |
===========================================================================

Inferred memory devices in process
	in routine LSU line 788 in file
		'../source/Core-1/memory/LoadStoreUnit.v'.
================================================================================
|    Register Name     |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
================================================================================
|   ldqBranchTag_reg   | Flip-flop |  128  |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqHead_reg      | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqTail_reg      | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqValid_reg     | Flip-flop |  32   |  N  | N  | N  | N  | N  | N  | N  |
|   ldqAddrValid_reg   | Flip-flop |  32   |  N  | N  | N  | N  | N  | N  | N  |
| precedingSTvalid_reg | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr2_reg     | Flip-flop |   2   |  N  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|       ldq_reg        | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   precedingST_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   ldqSizeofLD_reg    | Flip-flop |   2   |  N  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  13   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  19   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  30   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  15   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  17   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  17   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  15   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  30   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  19   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  13   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  28   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  21   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  11   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  26   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  23   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   9   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  24   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  25   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  10   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  22   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  27   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  12   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  20   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  29   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  14   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  18   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  31   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     ldqAddr1_reg     | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
================================================================================

Inferred memory devices in process
	in routine LSU line 1132 in file
		'../source/Core-1/memory/LoadStoreUnit.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    ldqCount_reg     | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine LSU line 1147 in file
		'../source/Core-1/memory/LoadStoreUnit.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     stqHead_reg     | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|  stqBranchTag_reg   | Flip-flop |  128  |  Y  | N  | N  | N  | N  | N  | N  |
|     stqTail_reg     | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqValid_reg     | Flip-flop |  32   |  N  | N  | N  | N  | N  | N  | N  |
|  stqAddrValid_reg   | Flip-flop |  32   |  N  | N  | N  | N  | N  | N  | N  |
|  stqCommitPtr_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|     stqData_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr2_reg     | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   stqSizeofST_reg   | Flip-flop |   2   |  N  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    stqAddr1_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|   followingLD_reg   | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine LSU line 1518 in file
		'../source/Core-1/memory/LoadStoreUnit.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    stqCommit_reg    | Flip-flop |  32   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine LSU line 1557 in file
		'../source/Core-1/memory/LoadStoreUnit.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    stqCount_reg     | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|     LSU/269      |   32   |    4    |      5       | N  |
|     LSU/270      |   32   |   30    |      5       | N  |
|     LSU/270      |   32   |    4    |      5       | N  |
|     LSU/271      |   32   |   32    |      5       | N  |
|     LSU/323      |   32   |    8    |      5       | N  |
|     LSU/335      |   32   |   10    |      5       | N  |
|     LSU/389      |   32   |    1    |      5       | N  |
|     LSU/410      |   32   |   32    |      5       | N  |
|     LSU/508      |   32   |    1    |      5       | N  |
|     LSU/518      |   32   |    7    |      5       | N  |
|     LSU/596      |   4    |   64    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'ActiveList'. (HDL-193)
Warning:  ../source/Core-1/retire/ActiveList.v:464: signed to unsigned conversion occurs. (VER-318)

Statistics for case statements in always block at line 502 in file
	'../source/Core-1/retire/ActiveList.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           573            |    auto/auto     |
===============================================
$display output: TRAP Instruction is being committed

Inferred memory devices in process
	in routine ActiveList line 748 in file
		'../source/Core-1/retire/ActiveList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     tailAL_reg      | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine ActiveList line 765 in file
		'../source/Core-1/retire/ActiveList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     headAL_reg      | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine ActiveList line 780 in file
		'../source/Core-1/retire/ActiveList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| activeListCount_reg | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine ActiveList line 796 in file
		'../source/Core-1/retire/ActiveList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    targetPC_reg     | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|    recoverPC_reg    | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|   exceptionPC_reg   | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|   recoverFlag_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|   mispredFlag_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|  exceptionFlag_reg  | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'ArchMapTable'. (HDL-193)
Warning:  ../source/Core-1/retire/ArchMapTable.v:227: signed to unsigned conversion occurs. (VER-318)

Inferred memory devices in process
	in routine ArchMapTable line 219 in file
		'../source/Core-1/retire/ArchMapTable.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   recoverCnt_reg    | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'BTB'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)

Statistics for case statements in always block at line 156 in file
	'../source/Core-1/fetch/BTB.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           158            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 207 in file
	'../source/Core-1/fetch/BTB.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           217            |    auto/auto     |
===============================================
Presto compilation completed successfully.
Information: Building the design 'BranchPrediction'. (HDL-193)

Statistics for case statements in always block at line 120 in file
	'../source/Core-1/fetch/BranchPrediction_2-bit.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           122            |    auto/auto     |
===============================================

Inferred memory devices in process
	in routine BranchPrediction line 178 in file
		'../source/Core-1/fetch/BranchPrediction_2-bit.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   wr_counter_reg    | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|     wr_dir_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|      wr_en_reg      | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|    wr_index_reg     | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'RAS'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)

Statistics for case statements in always block at line 65 in file
	'../source/Core-1/fetch/RAS.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            68            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine RAS line 91 in file
		'../source/Core-1/fetch/RAS.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|      stack_reg      | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
|       tos_reg       | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
|     tos_CP_reg      | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|      RAS/55      |   32   |   32    |      5       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'L1ICache'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'CtrlQueue'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)

Statistics for case statements in always block at line 159 in file
	'../source/Core-1/fetch/CtrlQueue.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           173            |    auto/auto     |
===============================================

Statistics for case statements in always block at line 295 in file
	'../source/Core-1/fetch/CtrlQueue.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           322            |     no/auto      |
|           350            |    auto/auto     |
===============================================

Inferred memory devices in process
	in routine CtrlQueue line 256 in file
		'../source/Core-1/fetch/CtrlQueue.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    commitPtr_reg    | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
|     headPtr_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine CtrlQueue line 272 in file
		'../source/Core-1/fetch/CtrlQueue.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    ctrlCount_reg    | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine CtrlQueue line 295 in file
		'../source/Core-1/fetch/CtrlQueue.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     tailPtr_reg     | Flip-flop |   4   |  Y  | N  | N  | N  | N  | N  | N  |
|  ctiqCommitted_reg  | Flip-flop |  16   |  N  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo1_reg    | Flip-flop |  33   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
|    ctiqInfo0_reg    | Flip-flop |  34   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|  CtrlQueue/106   |   16   |   64    |      4       | N  |
|  CtrlQueue/107   |   16   |    2    |      4       | N  |
|  CtrlQueue/109   |   16   |    2    |      4       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'PreDecode_PISA'. (HDL-193)

Statistics for case statements in always block at line 48 in file
	'../source/Core-1/decode/PreDecode_PISA.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            63            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'Decode_PISA'. (HDL-193)
$display output: DSW instruction occured, PC:????????

Statistics for case statements in always block at line 101 in file
	'../source/Core-1/decode/Decode_PISA.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           134            |    auto/auto     |
===============================================
Presto compilation completed successfully.
Information: Building the design 'SRAM_8R8W' instantiated from design 'InstructionBuffer' with
	the parameters "16,4,126". (HDL-193)
Warning: Cannot find the design 'SRAM_8R8W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SpecFreeList'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/rename/SpecFreeList.v:130: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:134: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:138: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:146: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:150: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:154: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:159: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:180: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:185: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:189: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:198: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/rename/SpecFreeList.v:203: signed to unsigned assignment occurs. (VER-318)

Statistics for case statements in always block at line 225 in file
	'../source/Core-1/rename/SpecFreeList.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           239            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine SpecFreeList line 194 in file
		'../source/Core-1/rename/SpecFreeList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  freeListHead_reg   | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
|   freeListCnt_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine SpecFreeList line 415 in file
		'../source/Core-1/rename/SpecFreeList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  freeListTail_reg   | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'RenameMapTable'. (HDL-193)

Statistics for case statements in always block at line 220 in file
	'../source/Core-1/rename/RenameMapTable.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           222            |    auto/auto     |
===============================================
Presto compilation completed successfully.
Information: Building the design 'SRAM_4R4W_PAYLOAD' instantiated from design 'IssueQueue' with
	the parameters "32,5,130". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_PAYLOAD' in the library 'WORK'. (LBR-1)
Information: Building the design 'CAM_4R4W' instantiated from design 'IssueQueue' with
	the parameters "32,5,7". (HDL-193)
Warning: Cannot find the design 'CAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'IssueQFreeList'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/issue/IssueQFreeList.v:145: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQFreeList.v:189: signed to unsigned assignment occurs. (VER-318)

Statistics for case statements in always block at line 184 in file
	'../source/Core-1/issue/IssueQFreeList.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           197            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine IssueQFreeList line 150 in file
		'../source/Core-1/issue/IssueQFreeList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     headPtr_reg     | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine IssueQFreeList line 165 in file
		'../source/Core-1/issue/IssueQFreeList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   issueQCount_reg   | Flip-flop |   6   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine IssueQFreeList line 184 in file
		'../source/Core-1/issue/IssueQFreeList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     tailPtr_reg     | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
| ISSUEQ_FREELIST_reg | Flip-flop |   5   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
=============================================================
|  block name/line   | Inputs | Outputs | # sel inputs | MB |
=============================================================
| IssueQFreeList/122 |   32   |    5    |      5       | N  |
| IssueQFreeList/123 |   32   |    5    |      5       | N  |
| IssueQFreeList/124 |   32   |    5    |      5       | N  |
| IssueQFreeList/125 |   32   |    5    |      5       | N  |
=============================================================
Presto compilation completed successfully.
Information: Building the design 'Select'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Presto compilation completed successfully.
Information: Building the design 'RSR2'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)

Inferred memory devices in process
	in routine RSR2 line 103 in file
		'../source/Core-1/issue/RSR.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  granted2Dest_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|   branchMask2_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|  validPacket0_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|  granted0Dest_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|   branchMask0_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|  validPacket1_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
|  granted1Dest_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|   branchMask1_reg   | Flip-flop |   7   |  Y  | N  | N  | N  | N  | N  | N  |
|  validPacket2_reg   | Flip-flop |   1   |  N  | N  | N  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine RSR2 line 138 in file
		'../source/Core-1/issue/RSR.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|    RSR_CALU_reg     | Flip-flop |  14   |  Y  | N  | N  | N  | N  | N  | N  |
| RSR_CALU_VALID_reg  | Flip-flop |   2   |  Y  | N  | N  | N  | N  | N  | N  |
|   BRANCH_MASK_reg   | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|     RSR2/99      |   4    |    2    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'SRAM_8R4W_PIPE' instantiated from design 'RegRead' with
	the parameters "96,7,32". (HDL-193)
Warning: Cannot find the design 'SRAM_8R4W_PIPE' in the library 'WORK'. (LBR-1)
Information: Building the design 'FU0'. (HDL-193)
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|     FU0/105      |   4    |    1    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'FU1'. (HDL-193)
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|     FU1/107      |   4    |    1    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'FU2'. (HDL-193)
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|     FU2/113      |   4    |    1    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'FU3'. (HDL-193)
Statistics for MUX_OPs
===========================================================
| block name/line  | Inputs | Outputs | # sel inputs | MB |
===========================================================
|     FU3/110      |   4    |    1    |      2       | N  |
===========================================================
Presto compilation completed successfully.
Information: Building the design 'ForwardCheck'. (HDL-193)

Statistics for case statements in always block at line 43 in file
	'../source/Core-1/execute/ForwardCheck.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            60            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine ForwardCheck line 43 in file
		'../source/Core-1/execute/ForwardCheck.v'.
===========================================================================
|    Register Name    | Type  | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
|     dataOut_reg     | Latch |  32   |  Y  | N  | N  | N  | -  | -  | -  |
===========================================================================
Presto compilation completed successfully.
Information: Building the design 'L1DataCache'. (HDL-193)

Statistics for case statements in always block at line 53 in file
	'../source/Core-1/memory/L1DataCache.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            60            |     no/auto      |
|           107            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine L1DataCache line 53 in file
		'../source/Core-1/memory/L1DataCache.v'.
===========================================================================
|    Register Name    | Type  | Width | Bus | MB | AR | AS | SR | SS | ST |
===========================================================================
|     rdData_reg      | Latch |  32   |  Y  | N  | N  | N  | -  | -  | -  |
===========================================================================
Presto compilation completed successfully.
Information: Building the design 'DispatchedLoad'. (HDL-193)

Statistics for case statements in always block at line 73 in file
	'../source/Core-1/memory/DispatchedLoad.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           104            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'DispatchedStore'. (HDL-193)

Statistics for case statements in always block at line 73 in file
	'../source/Core-1/memory/DispatchedStore.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           101            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'CommitLoad'. (HDL-193)

Statistics for case statements in always block at line 48 in file
	'../source/Core-1/memory/CommitLoad.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            59            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'CommitStore'. (HDL-193)

Statistics for case statements in always block at line 50 in file
	'../source/Core-1/memory/CommitStore.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            61            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,55". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,8". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,32". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,1". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_AMT' instantiated from design 'ArchMapTable' with
	the parameters "34,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_AMT' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_1R1W' instantiated from design 'BTB' with
	the parameters "1024,10,17". (HDL-193)
Warning: Cannot find the design 'SRAM_1R1W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_1R1W' instantiated from design 'BTB' with
	the parameters "1024,10,35". (HDL-193)
Warning: Cannot find the design 'SRAM_1R1W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_2R1W_HY' instantiated from design 'BranchPrediction' with
	the parameters "32768,15,2,4,2". (HDL-193)
Warning: Cannot find the design 'SRAM_2R1W_HY' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_FREELIST' instantiated from design 'SpecFreeList' with
	the parameters "62,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_FREELIST' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_8R4W_RMT' instantiated from design 'RenameMapTable' with
	the parameters "34,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_8R4W_RMT' in the library 'WORK'. (LBR-1)
Information: Building the design 'FreeIssueq'. (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/issue/IssueQFreeList.v:424: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQFreeList.v:424: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQFreeList.v:429: signed to unsigned conversion occurs. (VER-318)
Warning:  ../source/Core-1/issue/IssueQFreeList.v:429: signed to unsigned conversion occurs. (VER-318)

Inferred memory devices in process
	in routine FreeIssueq line 440 in file
		'../source/Core-1/issue/IssueQFreeList.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   freedVector_reg   | Flip-flop |  32   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'Encoder' instantiated from design 'Select' with
	the parameters "32,5". (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:  ../source/Core-1/issue/IssueQSelect.v:303: signed to unsigned assignment occurs. (VER-318)
Presto compilation completed successfully.
Information: Building the design 'selectBlock_8'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'selectBlock_4'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'Simple_ALU'. (HDL-193)
Warning:  ../source/Core-1/execute/Simple_ALU.v:168: unsigned to signed assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Simple_ALU.v:169: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Simple_ALU.v:174: unsigned to signed assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Simple_ALU.v:175: signed to unsigned assignment occurs. (VER-318)

Statistics for case statements in always block at line 45 in file
	'../source/Core-1/execute/Simple_ALU.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            60            |     no/auto      |
|           180            |    auto/auto     |
|           190            |    auto/auto     |
===============================================
Presto compilation completed successfully.
Information: Building the design 'Complex_ALU'. (HDL-193)
Warning:  ../source/Core-1/execute/Complex_ALU.v:48: unsigned to signed assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:49: unsigned to signed assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:64: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:65: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:70: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:71: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:88: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:89: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:94: signed to unsigned assignment occurs. (VER-318)
Warning:  ../source/Core-1/execute/Complex_ALU.v:95: signed to unsigned assignment occurs. (VER-318)

Statistics for case statements in always block at line 51 in file
	'../source/Core-1/execute/Complex_ALU.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            61            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'Ctrl_ALU'. (HDL-193)

Statistics for case statements in always block at line 56 in file
	'../source/Core-1/execute/Ctrl_ALU.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            71            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'AGEN'. (HDL-193)

Statistics for case statements in always block at line 45 in file
	'../source/Core-1/execute/AGEN.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            58            |     no/auto      |
===============================================
Presto compilation completed successfully.
Information: Building the design 'selectFromBlock_0'. (HDL-193)

Statistics for case statements in always block at line 488 in file
	'../source/Core-1/issue/IssueQFreeList.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           490            |    auto/auto     |
===============================================
Presto compilation completed successfully.
Information: Building the design 'PriorityEncoder' instantiated from design 'selectBlock_8' with
	the parameters "8". (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Presto compilation completed successfully.
Information: Building the design 'PriorityEncoder' instantiated from design 'selectBlock_4' with
	the parameters "4". (HDL-193)
Warning:  Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Presto compilation completed successfully.
Warning: Design 'FABSCALAR' has '10' unresolved references. For more detailed information, use the "link" command. (UID-341)
1
